As disclosed in Japanese Published Unexamined Patent Application Nos. Hei 08-149308 and Hei 09-027752, an image coding method for bit plane coding (entropy coding in bit-plane units) wavelet-transformed coefficient values has been proposed, and this method is adopted in the JPEG 2000 coding system being standardized by the ISO.
FIG. 2 shows a generalized flow of processing by the image coding system. In FIG. 2, an input pixel value is a multivalue data where each pixel value is represented by plural bits. If the value 20 is transform-encoded (21) by wavelet transform (or other transform-coding method such as DCT), the output becomes a coefficient value (22). The coefficient value 22 is also multivalue data. Although omitted in this figure, the coefficient value 22 may be quantized in accordance with necessity. Next, the coefficient value 22 (or quantized value) is entropy-encoded (23) in bit plane units, and coded data (24) is obtained.
In the bit plane coding, as multivalue data as an input must be processed in bit plane units, processing to divide the input multivalue data array into individual bit planes is logically required. FIG. 3 shows an example of processing to divide an array 30 of 4×4 4-bit coefficient value into bit planes 31 to 34.
Next, actual execution of bit plane coding on multivalue data, which has been read from a memory (into a register) by a coding processor, will be considered.
In this example, a data bus width of the memory is w bits, a bit width (depth) of the multivalue data is d bits, and d-bit multivalue data are stored on the memory without any gap.
When the coding processor directly loads the data into the memory, w-bit data read by one loading includes w/d multivalue data of d-bit. In only one bit plane of interest, only w/d bits from the bit plane are included, and if this bit plane is subjected to the following processing, the remaining (w−w/d) bits are wasteful bits. Accordingly, to perform bit plane coding processing on one bit plane, it is necessary to repeat loading of bit plane and to mask unnecessary bits to extract necessary bits.
FIG. 4 shows an example in the above-described coding processing where a register width of the coding processor (1 word) is 32 bits, the memory data bus width is 32 bits, and the multivalue data bit width is 8 bits. 8-bit multivalue data, more specifically, four multivalue data per 1 word, are stored in a memory 40, and 4×4 (=16) multivalue data construct one processing unit of bit plane coding. If a bit plane constructed with most significant bits (hatched portion in FIG. 4) of the multivalue data is subjected to bit plane coding, first, to load the four most significant bits 31, 23, 15 and 7 of data 0 to 3 into a register 41, 1-word load processing to load 1 word from an address 0 of the memory 40 is performed.
At this time, among the loaded data 0 to 3, only the above-described 4 bits are necessary but the other bit data are unnecessary for bit plane coding. Accordingly, to specify necessary bits, it is necessary to perform bit mask processing on the register 41 and extract necessary bits. Next, the load processing is performed to load the most significant bits of data 4 to 7, from an address 4 of the memory 40, and further, the load processing is performed to load the remaining bits in the currently-processed block from an address 8 of the memory 40, then from an address 12 of the memory 40. Thus the load processing must be performed 4 times in the entire processing block.
Further, when the bit plane of most significant bits has been processed and the process proceeds to the next bit plane, the load processing is performed 4 times and the bit mask processing is performed on the register 41, so as to extract necessary bits, as in the case of the bit plane of most significant bits. This processing is repeated to all the bit planes (8 bit planes in FIG. 3).
The conventional coding processing as described in the above example requires the coding processor to issue a large number of load instructions and perform mask processing many times, which disturbs improvement in efficiency and speed of the bit plane coding processing. Further, even if the above processing is realized by software, the result of processing is the same.
On the other hand, in the above-described Japanese Published Unexamined Patent Application Nos. Hei 08-149308 and Hei 09-027752, logical algorithms of bit plane coding are described, however, particular methods of realizing the coding are not described.